In modern superscalar processors, there are a large number of pipelines all trying to read from and write to a shared register file. However, it is difficult to implement a shared register file with a large number of read and write ports without reducing the clock speed.
One method to resolve this issue has been to implement register file caching. This uses multiple caches (unrelated to the memory caches in the system) to reduce the bandwidth on the shared register file. In such systems the number of writes to the register can be reduced using a write back caching system as physical registers can be removed from the cache when they are retired. However, these systems require some form of management to migrate data between caches which do not currently reside in the shared register file.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known processors.